[Journal
Papers | Conference papers]
Journal
Papers
- B.S. Liang, Y. C. Lee, W. C. Yeh and C. W. Jen, 2002 “ Index Rendering : Hardware-efficient Architecture for 3-D Graphics in Multimedia System “ accepted for publications in IEEE Trans. Multimedia
- B. S. Liang and C. W. Jen, 2002 “ Base Model Transmission for 3D Graphics in a Network Environment “ accepted for publication in IEICE Trans. Information and Systems
- T. H. Lin, T. H. Lee and C. W. Jen, 2002 “ Clumping Issues in ATM Switch Implementation “ accepted for publication in IEICE Trans. Information and Systems
- J. C. Tuan, T. S. Chang and C. W. Jen, 2002 “ On the Data Reuse and Memory Bandwidth analysis for Full Search Block matching VLSI Architecture “ IEEE Trans. Circuits and Systems for Video technology, Vol.12, No.1, pp.61-72
計畫編號: NSC-87-2215-E009-039
- B. S. Liang and C. W. Jen, 2001 “ Speedup Rendering Pipeline by Deferred Lighting and Triple Queue structure “ Electronics Letters, Vol.37, No.22 pp.1332-1333
計畫編號: NSC-89-2218-E009-085
- T. S. Chang and C. W. Jen, 2001 “ Hardware Efficient Pipelined Programmable FIR Filter Design “ IEE Proceeding : Computers and Digital Techniques, Vol.148, No.6, 227-232
計畫編號: NSC-85-2221-E009-056
- Y. C. Lee and C. W. Jen, 2001 “ Improved Quadratic Normal Vector Interpolation for Realistic Shading “ The Visual Computer, Vol.17, Issue 6, pp.337-352
計畫編號: NSC-89-2218-E009-085
- K. B. Lee and C. W. Jen, 2001 “ Design and Verification for Configurable Memory Controller- Memory Interface Socket Soft IP “ Journal of the Chinese Institute of Electrical Engineering, Vol. 8, No. 4, pp.309-323
計畫編號: NSC-89-2215-E009-003
- B. S. Liang and C. W. Jen, 2000 “ Computation-Effective 3D Graphics Rendering Architecture for Embedded Multimedia System “ IEEE Trans. Consumer Electronics, Vol. 46, No. 3, pp.735-743
計畫編號: NSC-89-2218-E009-085
- W. C. Yeh and C.W. Jen, 2000 “High-Speed Booth Encoded Parallel Multiplier Design” IEEE Trans. Computers, Vol.49, No.7, pp.692-701
計畫編號: NSC-88-2215-E-009-066
- T. S. Chang, J. I. Guo and C. W. Jen, 2000 “ Hardware Efficient DFT Designs
with Cyclic Convolution and Subexpression Sharing” IEEE Trans. Circuits and Systems, II Analog and Digital Signal Processing, Vol.47, No.9
計畫編號: NSC-88-2215-E-009-066
- T. S. Chang, C. S Kung and C. W. Jen, 2000 “A Simple Processor Core Design for DCT/IDCT” IEEE Trans. Circuits and Systems for Video Technology, Vol.10, No.3, pp.439-447
計畫編號: NSC-86-2221-E-009-014
- T. S. Chang, Y. H. Chu and C. W, Jen, 2000 “ Low-Power Filter Realization
with Differential Coefficients and Inputs” IEEE Trans. Circuits and Systems,
II Analog and Digital Signal Processing, Vol.47, No.2, pp.137-145
計畫編號: NSC-88-2215-E-009-066
- T. S. Chang and C. W. Jen, 1999 “Hardware-Efficient Implementations for
Transforms in Programmable Logic Device” IEE Proceedings: Computers and
Digital Techniques, Vol.146, No.6 pp.309-315
計畫編號: NSC-87-2215-E-009-039
- T. S. Chang, C. W. Jen and C. S. Chen, 1999 "A New Distributed Arithmetic
Algorithm and its Applications to IDCT” IEE Proceedings: Circuits, Device and Systems, Vol.146, No.4 pp159-163
計畫編號: NSC-86-2221-E-009-014
- C.C.Yang, T.S.Chang and C.W.Jen, 1998 "A NEW RSA Cryptosystem
Hardware Design based on Montegomery's Algorithm" IEEE Trans on
Circuits and System, II Analog and Digital Signal Processing,Vol.45,No.7
pp.908-913.
計畫編號:NSC-85-2215-E-009-057
- C.H.Lin and C.W.Jen, 1998 "Low Power Parallel Huffman Decoding"
Electronics Letter, Vol.34,No.3,pp.240-241
計畫編號:NSC-85-2221-E-009-056
- C.M.Huang, T.S.Chang and C.W.Jen, 1997 "A Multiplierless Reconfigurable
Resizer for Image Display " IEEE Trans on Consumer Electronics,
Vol.43,No.3,pp.826-832.
計畫編號:NSC85-2221-E009-056
- T. S. Chang and C. W. Jen, 1997 "On-chip Memory Module Designs for Video Signal Processing" IEE Proceedings:Circuits, Devices and Systems, Vol.144,No.3,pp.138-144
計畫編號:NSC-83-0404-E009-00-029
- C. H. Lin, C. M. Chen and C. W. Jen, 1996 "Low Power Design for MPEG-2 Video Devoder" IEEE Trans on Consumer Electronics, Vol.42,
No.3,pp.513-521
計畫編號:NSC-84-2622-E009-009
- H. R. Lee, C. W. Jen and C. M. Liu, 1996 "A New Hardware-Efficient Architecture for Programmable FIR Filters" IEEE Trans on Circuits and Systems, II:Analog and Digital Signal Processing, Vol.43,No.9, pp.637-644
計畫編號:NSC-83-0404-E-009 -041
- J. W. Yeh, W. J. Cheng and C. W. Jen, 1996 "VASS-A VLSI Array System Synthesizer" Journal of VLSI Signal Processing, Vol.12,pp.135-158
計畫編號: NSC-81-0404-E-009-134
- J. I. Guo, C. S. Chen and C. W. Jen, 1995 "Unified Array Architecture for Discrete Cosine Transform and their Inverses" Electronics Letters Vol.31, No.21, pp.1811-1812.
計畫編號: NSC-82-0404-E-009-225
- C. L. Chen, B. S. Liang and C. W. Jen, 1995 "A Low-Cost Raster Engine for Video Game, Multimedia PC and Interactive TV" IEEE Trans on Consumer Electronics, Vol.41, No.3, pp.724-730.
計畫編號: NSC-83-0404-E-009-041
- S. F. Chang, J. H. Hwang and C. W. Jen, 1995 "Scalable Array Architecture Design for Full Search Block Matching" IEEE Trans on Circuits and Systems for Video Technology, Vol.5, No.4, pp.332-343.
計畫編號:NSC-82-0404-E-009 -225
- J.I.Guo, C.M.Liu and C.W.Jen, 1995, "A Novel CORDIC-Based Array Architecture for the Multi-Dimensional Discrete Hartley Transform" IEEE Trans on Circuits and Systems II:Analog and Digital Signal Processing, Vol.42, No5, pp.349-355.
計畫編號:NSC-80-0404-E009-039
- C.L.Lee and C.W.Jen, 1994, "CMOS Threshold Gate and Networks for Order Statistic Filtering" IEEE Trans on Circuits and Systems. I. Fundamental Theory and Applications, Vol.41, No.6 pp.453-456.
計畫編號:NSC-80-0404-E-009 -013
- C.P.Lan and C.W.Jen, 1994, "Efficient Time Domain Synthesis of Pipelined Recursive Filters" IEEE Trans on Circuits and Systems, II . Analog and Digital Signal Processing, Vol.41. No.9 pp.618-622.
計畫編號:NSC-81-0404-E-009 -137
- S.F.Chang, C.L.Lee and C.W.Jen, 1994, "A Motion Detection Scheme for Motion Adaptive Proscan Conversion", Signal Processing: Image Communication. Vol.6, pp.349-356.
計畫編號:NSC-81-0404-E-009 -134
- H.R.Lee, C.W.Jen and C.M.Liu, 1993, "On the Design Automation of the Memory-Based VLSI Architectures for FIR Filters" IEEE Trans on Consumer Electronics, Vol. 39,No. 3, pp.619-629.
計畫編號:NSC-82-0404-E009-224
- C.L.Lee and C.W.Jen, 1993, "Binary Partition Algorithms and VLSI Architectures for Median and Rank Order Filtering" IEEE Trans on Signal Processing Vol.41, No.9. pp.2937-2942.
計畫編號:NSC-79-0404-E009-27
- J.I.Guo, C.M.Liu and C.W.Jen, 1993, "A New Array Architecture for Prime-Length Discrete Cosine Transform" IEEE Trans on Signal Processing, Vol.41, No.1. pp. 436-442.
計畫編號:NSC-80-0404-E009-39
- 16 journal papers published before 1993.
Conference
Papers
- T. J. Lin and C. W. Jen, 2001, “ An Efficient 2-D DWT Architecture via Resource Cycling “ IEEE ISCAS Sydney, pp.914-917
- Y. C. Lee and C. W, Jen, 2001 “ Arbitrarily Scalable Edge-preserving Interpolation for 3-D Graphics and Video Resizing “ IEEE ISCAS Sydney, pp.317-320
- Y. L. Hsiao and C. W. Jen, 2001 “ Power Modeling and Low Power Design of Content Addressable Memories “ IEEE ISCAS, Sydney
- T. J. Lin and C. W. Jen, 2001 “ Formal Equivalence Checking of Folded architectures “ WSES/IEEE World Multiconference on Circuits, Systems, communications and Computers ( CSCC ) Crete, pp.292-296
- Y. C, Lee and C. W. Jen, 2001 “ Top-down Design of High-performance Arbitrarily Scalable Edge-preserving Interpolation “ VLSI Design/CAD Symposium, Hsinchu
- C. L. Su and C. W. Jen, 2001, “ Motion Estimation with MSD-first Processing “ VLSI Design/CAD Symposium, Hsinchu
- T. J. Lin, T. S. Yang and C. W. Jen, 2001 “ Co-processing Data-path Generation in Configurable DSP Platform “ VLSI Design/CAD Symposium, Hsinchu
- W, C. Yeh and C. W. Jen, 2000, “ On the Study of Logarithmic Time Parallel Adders “ IEEE Workshop on Signal Processing Systems, pp.459-466
- I. Y. Hsiao and C. W. Jen, 2000, “A New Hardware Design and FPGA Implementation for Internet Routing towards IP over WDM and Terabit Routers” IEEE ISCAS, Geneva, Switzerland, pp.I387-I390
- C. L. Su and C. W. Jen, 2000 “Motion Estimation using On-Line Arithmetic” IEEE ISCAS, Geneva, Switzerland, pp.I683-I686
- B. S. Liang, W. C. Yeh, Y. Z. Lee and C. W. Jen, 2000 “Deferred Lighting: A Computation-Efficient Approach for Real-time 3D Graphics” IEEE ISCAS, Geneva, Switzerland, pp.IV657-IV660
- W. C. Yeh and C. W. Jen, 2000 “A High Performance Carry-Save to Signed-Digit Recoder for Fused Addition-Multiplication” IEEE ICASSP, Istanbul, Turkey, pp.3259-3262
- Y. C. Lee and C. W. Jen, 2000 “On-Line Polygon Refining using A Low Computation Subdivision Algorithm” Proceedings of Geometrical Modeling and Processing, Hong Kong, pp209-219
- T. J. Lin and C. W. Jen, 2000 “Data Stream Generation for Concurrent Computation in VLSI Signal Processors” 16th World Computer Congress, ICSP, Beijing, China, pp.587-590
- Y. L. Hsiao and C. W. Jen, 2000 “On the Design of RAM-based Ipv4 Engine IP” 11th VLSI Design/CAD Symposium, Kenting, Taiwan, pp.197-200
- Y. C. Lee and C. W. Jen, 2000 “Dynamic Buffer Management and IP Design of High Speed Serial Bus” 11th VLSI Design/CAD Symposium, Kenting, Taiwan, pp.201-204
- T. S. Chang, J. I. Guo and C. W. Jen, 1999 “A Compact IDCT Processor for HDTV Applications” IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, pp.151-158
- K. B. Lee, C.-H. Lin and C.-W. Jen, 1999, “Bus Buffer Modeling and Optimization in Vedio Processing IP“, The 6th IEEE International Conference on Electronics, Circuits and Systems, Pafos, Cyprus
- B. S. Liang, Y. C. Lee, W. C. Yeh and C.W.Jen, 1999, "Index Rendering: A Hardware Efficient Architecture for 3-D Graphics”, 10th VLSI Design/CAD Symposium, Taiwan, pp.137-140
- C. C. Yang and C.W.Jen, 1999, "A Multithread Media Processor Core with Dynamic Scheduling", 10th VLSI Design/CAD Symposium, Taiwan, pp.145-148
- H. C. Chen, J. I. Guo and C.W.Jen, 1999, "Low Power Module Designs for Video Codec Systems", 10th VLSI Design/CAD Symposium, Taiwan, pp.275-278
- J.C. Tuan and C.W.Jen, 1998, "An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement", IEEE 8th Great Lake Symposium on VLSI, Louisiana, U.S.A. pp.152-156
- T.S. Chang and C.W.Jen, 1998, "Low Power FIR Filter Realization with Differential Coefficients and Input" IEEE. ICASSP, Seattle, U.S.A. pp.3009-3012
- T.S. Chang and C.W.Jen, 1998, "Hardware Efficient Transform Designs with Cyclic Formulation and Subexpression Sharing" IEEE. ISCAS. Montery, U.S.A
- J.W.Yeh and C.W.Jen, 1998, "Hardware-Software Interactions on a Media Processor IC" 9th VLSI Design/CAD Symposium, Taiwan, pp.411-414
- Y.P. Niou, B. S. Liang and C.W.Jen, 1998, "Memory Interfaces in 3D Graphics Processor" 9th VLSI Design/CAD Symposium, Taiwan, pp.423-426
- C.L.Su, Y.T.Hwang and C.W.Jen, 1997 "A Novel Recursive Digital Filter Based on Signed Digit Distributed Arithmetic", IEEE ISCAS, Hong Kong, pp.2104-2107
- B.S.Liang, Y.C.Nieh and C.W.Jen, 1997 "An Area and Time Efficient Adder for Multiple Additions With Different Word-Length", IEEE ISCAS, Hong Kong, pp.2112-2115
- J.W.Yeh and C.W.Jen, 1997 "Functional Flow Graph Model and its Application to the Hardware/Software Codesign for Video Coding Sustems”, Fourth Asia-Pacific Conference on Hardware Description Languages, Taiwan, pp.136-139
- B.S.Liang, Y.C.Nieh, C.W.Jen and Gene Chuang, 1997 "A Hardware-Efficient Architecture for 3D Graphics Processor" Int. Symp. on VLSI Technology, Systems, and Applications, Taipei, pp.88-92
- J.W.Yeh and C.W.Jen, 1997 "Specification Capture and Analysis for Hardware/Software Codesign" 8th VLSI Design/CAD Symposium, Taiwan, pp.221-224
- Y.C.Nieh, B.S.Liang and C.W.Jen, 1997 "A Cost Effective Hardware for Texture Mapping" 8th VLSI Design/CAD Symposium, Taiwan, pp.89-92
- C. S. Chen, T. S. Chang and C. W. Jen, 1996 "The IDCT Processor on the Adder-Based Distributed Arithmetic" IEEE Symposium on VLSI Circuits, Honolulu, U.S.A. pp.36-37
- C. C. Chen and C. W. Jen, 1996 "A Programmable Concurrent Video Signal Processor" IEEE International Conference on Image Processing, Lausanne, Switzerland
- C. C. Yang and C. W. Jen, 1996 "The IC Design of A High Speed RSA Processor "IEEE APCCAS'96, Seoul, Korea
- Y. C. Yang and C. W. Jen, 1996 "Memory Model and Its Applications in Computer Graphics" 7th VLSI Design /CAD Symposium, Taiwan, pp.15-18
- C. M. Huang and C. W. Jen, 1995 "The Design on Image Resizer for Multiple Windows" HD-MEDIA Technology and Applications Workshop, TAIWAN, pp.OA2-01∼OA2-08.
- C. H. Lin and C. W. Jen, 1995 "On the Bus Arbitration for MPEG 2 Video Decoder" Int. Symp. on VLSI Technology, Systems and Applications, pp.201-205.
- C. M. Huang and C. W. Jen, 1995 "An Image Resizing IC for Multiple Window Display" Int. Symp. on VLSI Technology, Systems and Applications, pp.214-218.
- T. S. Chang and C. W. Jen, 1995 "Embedded Memory Module Design for Video Signal Processing" IEEE Workshop on VLSI Signal Processing, Osaka, Japan.
- C. Chen and C. W. Jen, 1995 "A 2D IDCT Processor Based on Adder-based Distributed Arithmetic" The 6th VLSI Design/CAD Symposium, Chiayi, pp.225-228.
- H. R. Lee and C. W. Jen, 1994 "Hardware Sharing in Tree-Structured QMF Banks" IEEE APCCAS'94, TAIWAN pp.4c.4.1-4c.4.6.
- C. L. Chen, C. H. Lin, H. R. Lee and C. W. Jen, 1994 "A Raster Engine for Computer Graphics and Image Composition" IEEE APCCAS'94, TAIWAN, pp. 4c.7.1-4c.7.6.
- C. L. Chen, C. H. Lin and C. W. Jen, 1994, "A Hardware Kernel for Video Composition and Image Rasterization" HD-MEDIA Technology and Application Workshop, TAIWAN, pp. p01-11∼p01-16.
- S. J. Wen, C. H. Lin and C. W. Jen, 1994 "Design and Implementation of Cell Loss Recovery System for Video Communications" HD-MEDIA Technology and Application Workshop, TAIWAN, pp.p02-71∼p02-76.,
- H. R. Lee and C. W. Jen, 1994, "Hardware Sharing in Regular Structure Multirate Systems" 5th VLSI Design/CAD Symposium, TAIWAN. pp.60-65.
- T. S. Chang and C. W. Jen, 1994, "Application Specific On-Chip Memory Design" 5th VLSI Design/CAD Symposium, TAIWAN, pp.304-309.
- J.I.Guo and C.W.Jen, 1994, "A General Approach to Design VLSI Arrays for Multidimensional Discrete Hartley Transform" IEEE ISCAS, London, pp.4.235-4.238.
- J.I.Guo, C.M.Liu and C.W.Jen, 1994, "A Novel VLSI Array Design for the Discrete Hartley Transform using Cyclic Convolution" IEEE ICASSP'94, Adelaide, AUSTRALIA, pp.II 501-504.
- S.F.Chang, J.H.Hwang and C.W.Jen, 1993, "A Cascadable Chip for Full Search Block Matching" Int. Symp. Communication, Hsinchu, Taiwan. pp.24-10∼24-16.
- J.C.Fan, C.H.Lin and C.W.Jen, 1993, "A Reconfigurable Data Path for Video Applications," HD-Media Technology and Applications Workshop, Taipei, Taiwan, pp. S1-21-26.
- H.R.Lee, C.M.Liu, and C.W.Jen, 1993, "On the Design Automation of the Memory-Based VLSI Architecture for FIR Filters," IEEE ICCE, Chicago, U.S.A. pp.334-335.
- J.I.Guo, C.M.Liu, and C.W.Jen, 1993, "A Two-level Pipelined Systolic Array Chip for Computing the Discrete Cosine Transform," VLSI Technology, System, and Application Symposium, pp.199-203.
- C.W.Jn, C.H.Lin, and J.S.Hung, 1993, "A Two-level On-Chip Memory for Video Signal Processor," VLSI Technology, System, and Application Symposium, pp.353-357.
- C.L.Lee and C.W.Jen, 1993, "Device Programmable CMOS Threshold Gate for Order Statistic Filtering", IEEE Winter Workshop on Nonlinear Digital Signal Processing, Tampere, Finland,pp.5.2-1.1--5.2-1.5.
- Y.S.Lin, J.I.Guo, C.W.Jen and C.B.Shung, 1993, "A Multi-phase Shared Bus Structure for the Fast Fourier Transform", IEEE, ISCAS, Chicago, U.S.A. pp.1575-1578.
- J.J.Wang and C.W.Jen, 1993, "A High Throughput Systolic Design for QR Algorithm",IEEE, ISCAS, Chicago, U.S.A. pp.1742-1745.
- J.I.Guo, C.M.Liu and C.W.Jen, 1993, "A CORDIC-Based VLSI Array for Computing 2-D Discrete Hartley Transform", IEEE, ISCAS, Chicago, U.S.A. pp.1571-1574.
- J.S.Hung, C.H.Lin, and C.W.Jen, 1993, "A Novel Memory Architecture for Vieo Signal Processor", International Symposium on Fiber Optic Networks and Video Communications, Berlin, FRG.
- 41 conference papers presented before 1993.
Last updated in Mar 13, 2002