Announcements Course Information Handouts Labs & Projects Related Resources

 Last Update Jun 13

   

Announcements


[Announced on Jun  13] Project Part3已公布。

[Announced on May 23] 新增Lab08 ~ Lab10相關資料。

[Announced on Apr 26] 新增Lab07 相關資料。

[Announced on Apr 13] 第二次 Project Part 2已公布。

[Announced on Apr 13] 新增Project Part 1 參考文件。

[Announced on Apr 13] 新增Lab06 關於Integrator的參考文件兩份。

[Announced on Apr 12] 新增Lab06 Slides和說明文件。

[Announced on Apr 05] Project Part 1 新增H.264 Bitstream 視訊壓縮檔 test.264。

[Announced on Apr 04] Project Part 1 新增YUV Viewer軟體。

[Announced on Mar 14] 新增Lab02 參考文件兩份。

[Announced on Mar 08] 第一次Project講義資料已公布。

[Announced on Feb 24] 上課講義已放上網頁。

[Announced on Feb 20] 課程網頁已經公布。
 

 

Course Information

Overview

System on Chip (SoC) is composed of many functional modules such as processor, memory, digital IPs, analog/mixed signal modules, RF and interfaces on a single chip. This course gives an introduction to digital IP design, the on-chip bus and integration of SoC. A term project is required in the lab part of the course. The labs are designed under the ARM Developer Suite (ADS) and ARM Integrator development board environment.

Prerequisites

Cell-based VLSI Design
C/C++, Assembly
Synthesizable HDL Coding Skills

Instructor

Prof.  Tian-Sheuan Chang (張添烜)
ED406, (03)5731925
E-mail: tschang@twins.ee.nctu.edu.tw


 

 

 

Lecture Hours

15:40 ~ 17:30 Tue ( 2GH ) ED414

Lab Hours

17:30 ~ 21:20 Tue ( 2IJK ) ED414

Schedule and Grading

Schedule and Grading is updated on Feb 20  PDF | HTML

Teaching Assistants

Name Phone Room E-mail
張彥中 Yen-Chung Chang (03) 571-2121 ext. 54225 ED412 ycchang@twins.ee.nctu.edu.tw
鄭朝鐘 Chao-Chung Cheng (03) 571-2121 ext. 54243 ED427 fury@twins.ee.nctu.edu.tw
古君偉  Chun-Wei Ku (03) 571-2121 ext. 54243 ED427 sjerry@twins.ee.nctu.edu.tw
王裕仁 Yu-Jen Wang (03) 571-2121 ext. 54243 ED427 cosbe@twins.ee.nctu.edu.tw
吳錦木  Yen-Chung Chang (03) 571-2121 ext. 54243 ED427 woody@twins.ee.nctu.edu.tw

 

Handouts
1

Introduction to IP and SoC

Zipped PDF

2

Overview of ARM Processor and Instruction Sets

Zipped PDF

3

On-chip Bus

Zipped PDF

4

Overview of IP Core Design Flow

Zipped PDF

5

SoC Design Flow and Platform Based Design

Zipped PDF

6

SoC Design Case Study

Zipped PDF

 

Labs & Projects

Labs

1

Mar 01

Code Development Note Slide Code  

2

Mar 08

Debugging and Evaluation Note Slide Code Reference Documents

3

Mar 15

Core Peripherals and Std. I/O Note Slide Code  

4

Mar 22

On-chip BUS AHB-lite Note Slide Code  

5

Mar 29

Memory Issue (optional) Note Slide Code  

6

Apr 12

Virtual Prototyping Note Slide Code Reference Documents

7

Apr 26

Rapid Prototyping I Note Slide Code  

8

May 03

Seamless (optional) Note Slide Code  

9

May 10

Rapid Prototyping II Note Slide Code  

10

May 17

Real-time OS I Note Slide Code  

11

May 24

Real-time OS II Note Slide Code  

Projects

1

Mar 08

Project Part 1 Project Description  Zipped JM code  H.264 Overview
      YUV Viewer Software  H.264 Bitstream File  Reference Documents

2

Apr 13

Project Part 2 Project Description    

3

Jun 13 

Project Part 3 Project Description    

 

Related Resources

Course Forum

Please visit the board EE_SOCLab in the BBS site kulu.twbbs.org

ARM Application Note

Benchmarking with ARMulator ( Lab02 reference documents )

Writing Efficient C for ARMulator ( Lab02 reference documents )

ARM Integrator Checking ( Lab06 reference documents )

Using Integrator ( Lab06 reference documents )

How to disable  the cache ( Project part 1 reference documents )

ARM Related

ARM Architecture Reference Manual (ver. Jane 2000, E)
To complete your homework, you may need the information described in Part A of this document.
Proprietary Notice: This document is owned by ARM Limited and you can find one copy in ARM ADS CD. For convenience, we put it here.

AMBA Specification

Steve Furber,
"ARM System-on-chip Architecture," Addison-Wesley, 2000

Algorithms and Architectures

Keshab K. Parhi

"VLSI Digital Signal Processing Systems, Design and Implementation," John Wiely & Sons, 1999