SoC Design Lab

Spring, 2004

[ Course Information | Handouts | Lab Notes & Homeworks | Related Resources ]


[Announced on June 25]
SoC Design Lab 成績公佈,對成績有疑問的同學請在星期一4:00PM後找老師。

[Announced on May 14]
IP/SOC Verification投影片有新的更新,請到

[Announced on May 13]
Final Project 3已公告,6/3號要繳交最終完整報告,請記得上傳。

Project Demo時間為6/2和6/3號,一天八組,請到工四412找助教登記Demo時刻。

Project Presentation時間為6/9和6/16號原上課時段,請到工四412找助教登記順序。

[Announced on May 11]
更正:實驗 課已結束,讓各位同學進行 final project。

Project 2 繳交說明

Some notes on Project 3

[Announced on May 7]
Some notes on Project 2

[Announced on Apr. 28]
期中考將於5月26日 上課時間舉行。實驗部份佔30%,課程部份佔 70%。可帶任何參考資料。

[Announced on Feb. 23]

Course Information


System on Chip (SoC) is composed of many functional modules such as processor, memory, digital IPs, analog/mixed signal modules, RF and interfaces on a single chip. This course gives an introduction to digital IP design, the on-chip bus and integration of SoC. A term project is required in the lab part of the course. The labs are designed under the ARM Developer Suite (ADS) and ARM Integrator development board environment.


Cell-based VLSI Design
C/C++, Assembly
Synthesizable HDL Coding Skills


Prof.  Tian-Sheuan Chang (張添烜)
ED406, (03)5731925

《Lecture Hours》

17:40--18:30 Tue. & 10:10--12:00 Wed. (2Y, 3CD) New!!
10:10--12:00 Wed. & 15:40--16:30 Fri. (3CD, 5G) Original.

《Lab Hours》

18:30--21:20 Tue. (2IJK)

《Schedule and Grading》

Schedule and Grading is updated on Feb. 19  PDF | HTML


張彥中 Nelson Yen-Chung Chang (03) 571-2121 ext. 54225 ED412
秦浩雲 Hao-Yun Chin (03) 571-2121 ext. 54225 ED412
許惠錚 Hui-Cheng Hsu (03) 571-2121 ext. 54225 ED412
鄭朝鐘 Chao-Chung Cheng (03) 571-2121 ext. 54243 ED427

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  1. SoC Overview and ARM Integrator [Feb. 18] PDF
  2. ARM Processor Core and Instruction Sets [Feb. 24] PDF
  3. ARM Processor Architecture [Mar. 15] PDF
  4. SoC Design Flow [Mar. 15] PDF
  5. Platform-based Design [Mar. 15] PDF
  6. On-chip Bus [Mar. 15] PDF
  7. VCI and AMBA [Mar. 15] PDF
  8. SoC Design Process [Apr. 08] PDF
  9. Reusable RTL Coding Guidelines [Apr. 08] PDF
  10. Synthesis Guidelines [Apr. 08] PDF
  11. IP/SoC verification [May. 13] PDF
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Labs & Projects


  1. Code Development [Mar. 02] Note  Slide  Code
  2. Debugging and Evaluation [Mar. 09] Note  Slide  Code
  3. Core Peripherals and Std. I/O [Mar. 15] Note  Slide  Code  Appendix
  4. Memory Issues [Mar. 23] Note  Slide  Code
  5. On-chip Bus: AHB-Lite [Mar. 30] Note  Slide  Code
  6. Virtual Prototyping: ARMulator [Apr. 6] Note  Slide  Code  Using Integrator  Integrator Checking Procedures
  7. ASIC Logic [Apr. 13] Note  Slide  Code
  8. ASIC Logic 2 [Apr. 20] Note  Slide  Code
  9. Real-time OS [Apr. 27] Note  Slide  Code
  10. Real-time OS 2 [May 4] Note  Slide  Code


  1. Project Part 1 [Mar. 09] Project Description  Introduction to JPEG  Reference Code
  2. Project Part 2 [Apr. 08] Project Description  nLint Rules
  3. Project Part 3 [June. 03] Project Description Demo&Presentation Guide
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Related Resources

《Course Forum》

Questions? Problems?
Check the SoC Design Lab Forum

《Instrument Registration》

Register for the instruments
(coming soon)

《ARM Related》

ARM Architecture Reference Manual (ver. Jane 2000, E)
To complete your homework, you may need the information described in Part A of this document.
Proprietary Notice: This document is owned by ARM Limited and you can find one copy in ARM ADS CD. For convenience, we put it here.

AMBA Specification

Steve Furber,
"ARM System-on-chip Architecture," Addison-Wesley, 2000

《Algorithms and Architectures》

Keshab K. Parhi,
"VLSI Digital Signal Processing Systems, Design and Implementation," John Wiely & Sons, 1999

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VLSI Signal Processing Lab
Phone:+886-3-5712121 ext. 54225

新竹市大學路1001號 國立交通大學電子研究所 工程四館 412室
ED412R Institute of Electronics, National Chiao Tung University

If you have any questions or comments, please email to us.

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