IP Core Design
Sep. 2001

Prof. Chein-Wei Jen Prof. Chein-Wei Jen



> > > Introduction < < <
《內容》
「單晶片系統 (System on Chip – SoC)」是由Processor、Memory、Digital IPs、Analog/Mixed Signal Modules 、RF 與Interfaces 等功能模組在單晶片上建構成。本課程將介紹Digital IP 之設計,和在SoC 上之Bus 介面與整合關係。本課程包含授課與實驗,實驗部份是一個 期末專題,在ARM development system (Integrator)上完成。

《Prerequisites》
Cell-based VLSI Design
《Course Contents》
  • Introduction to IP and SoC
  • IP Core Design Flow
  • Algorithm and Architecture Explorations
  • VCI Standard and On-chip Bus
  • ARM Processor and Platform-based Design
  • IP Modeling and Verifications
  • Some Design Studies
  • 《Instructor》
        Prof. Chein-Wei Jen (任建葳 教授)
        ED406, (03)5731925
        E-mail: cwjen@twins.ee.nctu.edu.tw
    《Lectures》
        Mon. (10:10~12:00) and Wed. (9:00~9:50) in ED220
    《Course TA》
        Kun-Bin Lee (李坤儐)
        Jih Yiing Lin (林季穎)
    《Lab TAs》
    English Chinese Phone Email
    Kun-Bin Lee 李坤儐 03-5712121 EXT: 54225 kblee@yankees.ee.nctu.edu.tw
    Yuan-Chung Lee 李元仲 03-5712121 EXT: 54225 yzlee@yankees.ee.nctu.edu.tw
    Jih Yiing Lin 林季穎 03-5712121 EXT: 54243 fern@mail2000.com.tw
    Nelson Yen-Chung Chang 張彥中 03-5712121 EXT: 54243 ycchang@yankees.ee.nctu.edu.tw
    Tzung-Shian Yang 楊宗憲 03-5712121 EXT: 54243 tsyang@yankees.ee.nctu.edu.tw


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    > > > Handout < < <
      Chapter 1. Introduction      (2001.9.14)
      Chapter 2. ARM Processor Core and Instruction Sets     (2001.10.15)
      Chapter 3. VCI Interface, AMBA Bus and Platform-based Design      (2001.10.30)
      Chapter 4. IP Core Design, Modeling and Verification      (2001.11.10)
      Chapter 5. Algorithm and Architecture Exploration in IP Core Design      (2001.12.10)

     

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    > > > Lab & Homework < < <

        Introduction to Lab and Homework
        Test BMP file 1 (9.2MB): motorcycle (2048x1536)
             original source: http://www.csie.nctu.edu.tw/~hhchen/index783.html
        Test BMP file 2 (1.4MB): station (800x600)

    《Tentative Schedule》
       Overview
    Oct. 29, 2001 Lab 1. ARM-based system software development environment
    lab 1 handout will be presented on 2001.10.24.
    lab 1 manual for those students not attend the presentation.
    Homework 1
    Due: 2001.11.12
    Nov. 12, 2001 Lab 2. ARM-based system hardware development environment
    lab 2 handout and auxiliary file package
    ARM Integrator Checking
    Homework 2
    Due: 2001.11.26
    Nov. 26, 2001 Lab 3. IP Modeling
    lab 3 handout and auxiliary file package
    Homework 3
    Due: 2001.12.10
    Dec. 10, 2001 Lab 4. IP core design
    RTL Coding Guidelines
    lab 4 handout and auxiliary file package and updated information link
    Xilinx XCV2000e package
    Homework 4
    Due: 2001.12.24
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    > > > Related Information - Reading & Resources < < <

    《ARM》
         ARM Architecture Reference Manual (ver. Jane 2000, E)
           To complete your homework, you may need the information described in Part A of this document.
           Proprietary Notice: This document is owned by ARM Limited and you can find one copy in ARM ADS CD.
                                           For convenience shake, we put it here.
         AMBA Specification

    《JPEG》
         JPEG website
         JPEG related information: Digital Image Processing, Rafael C. Gonzalez and Richard E. Woods, 1993.

    《IP Authoring》
         IP measurement for reusability: OpenMORE
         Reuse guides: Reuse Methodology Manual for System-on-A-Chip Designs, by Michael Keating and Pierre
             Bricaud, 2ed. 1999
         FPGA Reuse Field Guide
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    VLSI Signal Processing Lab
    Phone:+886-3-5712121 EXT: 54225
    新竹市大學路1001號 國立交通大學電子研究所 工程四館 412室
    If you have any questions or comments, please email to us.